1. Field of the Invention
The present invention relates to a solid state image sensor and a method for manufacturing the same, and more specifically to a solid state image sensor having an unnecessary electric charge exhausting section formed adjacent to a horizontal electric charge transfer section, and a method for manufacturing the same.
2. Description of Related Art
A solid state image sensor, which has been conventionally widely incorporated as an image pickup means in a single-unit video camera recorder, is now increasing the number of pixels included therein, and at present, has started to be used, in place of an optical camera exposing a film, as an electronic still camera which converts optical information into an electric signal and stores the electric signal in a memory medium, to make it possible to produce a hard copy from the stored electric signal, or to reproduce the optical information on a monitor display screen.
The solid state image sensor as mentioned above, includes a photoelectric conversion section, and an electric charge transfer section for vertically and horizontally transferring a signal electric charge accumulated in the photoelectric conversion section. Actually, in addition to the signal electric charge which will become an essentially required video signal, there exists an unnecessary electric charge including an electric charge photoelectrically converted in an unnecessary period and an electric charge due to a current generated at a silicon-oxide film boundary. When the solid state image sensor is incorporated as the image pickup means in the single-unit video camera-recorder, even if the unnecessary electric charge is generated, the unnecessary electric charge will lower at an negligible level after a few frames, and therefore, the unnecessary electric charge will not become a large problem. However, when the solid state image sensor is used as the image pickup means of the electronic still camera, the unnecessary electric charge is superposed on the signal charge which should become the essentially required video signal, with the result that an image quality is deteriorated. In addition, if a substantial time is required to remove the unnecessary electric charge, there occurs a time delay from the moment a shutter button is triggered to the moment the shutter is actually opened and closed, with the result that a so-called shutter chance may be lost.
Therefore, differently from the solid state image sensor incorporated in the single-unit video camera-recorder, the solid state image sensor used as the image pickup means of the electronic still camera, is required to momentarily remove all unnecessary electric charges existing in the photoelectric conversion section and the vertical and horizontal electric charge transfer sections, at the same time as the shutter button is triggered.
As a means for removing the unnecessary electric charges, for example, Y. Ishihara et al proposes an "Interline CCD Image Sensor with Vertical Overflow Drain", in Journal of Society of Television of Japan, Vol. 37, No. 10, 1983, pages 782-787. In brief, in order to remove the unnecessary electric charges existing in the photoelectric conversion section, a P.sup.- semiconductor region having a low impurity concentration is formed directly under an N type semiconductor region constituting the photoelectric conversion section, and a reverse biasing is applied to an N.sup.-- semiconductor substrate so that an excess electric charge is removed into the N.sup.-- semiconductor substrate for a blooming suppression, and the N type semiconductor region itself is depleted so that all the signal electric charge is removed into the N.sup.-- semiconductor substrate.
In addition, the unnecessary electric charge existing in the horizontal electric charge transfer section, can be removed into a reset drain provided at an end of the horizontal electric charge transfer section in a conventional operation, since the horizontal electric charge transfer section can operate at a high speed.
On the other hand, in order to remove the unnecessary electric charge existing in the vertical electric charge transfer section, it is necessary to transfer at least one to a few frames.
For example, Japanese Patent Application Pre-examination Publication No. JP-A-02-205359 (the content of which is incorporated by reference in its entirety into this application, and an English abstract of JP-A-02-205359 is available from the Japanese Patent Office, and the content of the English abstract is also incorporated by reference in its entirety into this application), proposes one method for removing the unnecessary electric charge existing in the vertical electric charge transfer. In brief, an unnecessary electric charge exhausting section is provided adjacent to the horizontal electric charge transfer section, so that the unnecessary electric charge existing in the vertical electric charge transfer section is removed by transferring the unnecessary electric charge existing in the vertical electric charge transfer section in a forward direction.
Referring to FIG. 1, there is shown a layout diagram of the solid state image sensor having the unnecessary electric charge exhausting section provided adjacent to the horizontal electric charge transfer section. The shown solid state image sensor includes an image sensor section 100, which comprises a number of photoelectric conversion cells 101 (each of which is formed of, for example, a photodiodes, and each of which will be called a "photocell" hereinafter) arranged in the form of a matrix, a plurality of vertical electric charge transfer sections 103 each of which extends along a corresponding vertical column of photocells, and a number of transfer gates 102 each provided between a corresponding photocell and a corresponding adjacent vertical electric charge transfer section 103. The vertical electric charge transfer sections 103 are driven, by four-phase drive pulses .phi.V1to .phi.V4to transfer signal charges through the vertical electric charge transfer section.
The shown solid state image sensor also includes a horizontal electric charge transfer section 300 formed along lower ends of the vertical electric charge transfer sections 103 and connected to the lower ends of the vertical electric charge transfer sections 103 through vertical-horizontal junction sections 200. The horizontal electric charge transfer section 300 has one end connected through an electric charge detection section 301 to an output amplification section 302.
Furthermore, the shown solid state image sensor includes an unnecessary electric charge exhausting section 500 extending along the horizontal electric charge transfer section 300, and a potential barrier section 400 formed between the horizontal electric charge transfer section 300 and the unnecessary electric charge exhausting section 500, and an N.sup.+++ semiconductor region 501 formed at one end of the unnecessary electric charge exhausting section 500 and connected to a power supply voltage VD.
Referring to FIG. 2, there is shown an enlarged layout pattern diagram, in accordance with the prior art, of a portion confined by a two-dot chain line in FIG. 1, which shows a portion of a region including the potential barrier section 400 and the unnecessary electric charge exhausting section 500 formed adjacent to the horizontal electric charge transfer section 300. The shown portion includes a transfer channel 15 of the vertical electric charge transfer sections 103, a transfer channel 14 of the vertical-horizontal junction sections 200, an electric charge barrier region 5 and an electric charge storage region 6 of a transfer channel of the horizontal electric charge transfer section 300, a potential barrier region 11 of the potential barrier section 400, an unnecessary electric charge exhausting region 12 of the unnecessary electric charge exhausting section 500.
The shown portion also includes first horizontal electric charge transfer electrodes 17H1and 17H2formed of a first level polysilicon film, of the horizontal electric charge transfer section 300, second horizontal electric charge transfer electrodes 19H1and 19H2formed of a second level polysilicon film, of the horizontal electric charge transfer section 300, and a final stage vertical electric charge transfer electrode 19VL formed of the second level polysilicon film, of the vertical electric charge transfer section 300. Each of the first horizontal electric charge transfer electrodes 17H1and 17H2is connected to an adjacent one, in the same direction, of the second horizontal electric charge transfer electrodes 19H1and 19H2to constitute a transfer electrode pair The transfer electrode pairs are alternately driven with two-phase drive pulses .phi.H1and .phi.H2. Therefore, if the transfer electrode pair composed of the first and second horizontal electric charge transfer electrodes 17H1and 19H1is driven by .phi.H1, the transfer electrode pair composed of the first and second horizontal electric charge transfer electrodes 17H2and 19H2is driven by .phi.H2.
Referring to FIG. 3A, there is shown a diagrammatic sectional view taken along the line I--I shown in FIGS. 1 and 2. FIG. 3B is a potential profiles under the portion shown in FIG. 3A. On an N.sup.-- semiconductor substrate 1 having the impurity concentration of for example 2.0.times.10.sup.14 cm.sup.-3, there is formed a P-type well layer 2 having the impurity concentration of for example 1.0.times.10.sup.16 cm.sup.-3. On the P-type well layer 2, there are formed an N type semiconductor region 6 having the impurity concentration of for example 1.0.times.10.sup.17 cm.sup.-3, which constitutes the transfer channel 15 of the vertical electric charge transfer section 103, the transfer channel 14 of the vertical-horizontal junction section 200, and the electric charge storage region of the transfer channel of the horizontal electric charge transfer section, a first N semiconductor region 11 having the impurity concentration of for example 6.0.times.10.sup.16 cm.sup.-3, which constitutes the potential barrier region, an N.sup.++ semiconductor region 12 having the impurity concentration of for example 1.0.times.10.sup.18 cm.sup.-3, which constitutes the unnecessary electric charge exhausting section, and a P.sup.++ semiconductor region 4 having the impurity concentration of for example 1.0.times.10.sup.18 cm.sup.-3, which constitutes a device isolation section.
Furthermore, these regions are covered with a silicon oxide film (3, 16), on which there are formed a first horizontal electric charge transfer electrode 17H1formed of the first level polysilicon film, and the final stage vertical electric charge transfer electrode 19VL formed of the second level polysilicon film. The N.sup.++ semiconductor region 12 constituting the unnecessary electric charge exhausting section, is applied with a power supply voltage VD ordinarily on the order of 15 V through an N.sup.+++ semiconductor region (designated by Reference Numeral 13 in FIG. 5A) having the impurity concentration of for example 1.0.times.10.sup.20 cm.sup.-3 and formed at one end of the unnecessary electric charge exhausting section.
Referring to FIG. 4A, there is shown a diagrammatic sectional view taken along the line II--II shown in FIG. 1, for illustrating the prior art horizontal electric charge transfer section. FIG. 4B is a potential profiles under the portion shown in FIG. 4A when the drive clock .phi.H1is at a low level voltage VL and the drive clock .phi.H2is at a high level voltage VH, and FIG. 4C is a potential profiles under the portion shown in FIG. 4A when .phi.H1is VH and .phi.H2is VL. The P-type well layer 2 is formed on the N.sup.-- semiconductor substrate 1. On the P-type well layer 2, there are formed N type semiconductor regions 6 each constituting the electric charge storage region of the transfer channel of the horizontal electric charge transfer section, N.sup.- semiconductor regions 5 having the impurity concentration of for example 7.0.times.10.sup.16 cm.sup.-3, each constituting the electric charge barrier region of the transfer channel of the horizontal electric charge transfer section, N.sup.+++ semiconductor regions 8 and 9 constituting a floating diffused region and a reset drain region, respectively, and the P.sup.++ semiconductor region 4 constituting the device isolation section.
These regions are covered with a silicon oxide film (3, 16), on which there are formed the first horizontal electric charge transfer electrodes 17H1and 17H2formed of the first level polysilicon film, an output gate electrode 17OG formed of the first level polysilicon film, a reset gate electrode 17R formed of the first level polysilicon film, the second horizontal electric charge transfer electrodes 19H1and 19H2formed of the second level polysilicon film, and a second output gate electrode 19OG formed of the second level polysilicon film. The N.sup.++++ semiconductor region 9 constituting the reset drain region for the signal electric charge, is applied with the power supply voltage VD ordinarily on the order of 15 V.
Referring to FIG. 5A, there is shown a diagrammatic sectional view taken along the line III--III shown in FIG. 1, for illustrating the prior art unnecessary electric charge exhausting section. FIG. 5B is a potential profiles under the portion shown in FIG. 5A. The P-type well layer 2 is formed on the N.sup.-- semiconductor substrate 1. On the P-type well layer 2, there are formed an N.sup.++ semiconductor region 12 constituting the unnecessary electric charge exhausting section, an N.sup.+++ semiconductor region 13 formed at one end of the unnecessary electric charge exhausting section, and the P.sup.++ semiconductor region 4 constituting the device isolation section.
These regions are covered with a silicon oxide film (3, 16), on which there are formed the first horizontal electric charge transfer electrodes 17H1and 17H2formed of the first level polysilicon film, and the second horizontal electric charge transfer electrodes 19H1and 19H2formed of the second level polysilicon film. The N.sup.++ semiconductor region 12 constituting the unnecessary electric charge exhausting section, is applied with the power supply voltage VD ordinarily on the order of 15 V, through the N.sup.+++ semiconductor region 13 formed at the one end of the unnecessary electric charge exhausting section.
In an operation of the solid state image sensor having the above mentioned structure, as mentioned hereinbefore, the unnecessary electric charge existing in the photoelectric conversion cell 101, is removed, by forming the P.sup.- semiconductor region having a low impurity concentration directly under the N type semiconductor region constituting the photoelectric conversion cell, and by supplying the N.sup.-- semiconductor substrate 1 with a reverse biasing voltage (Vsub) which is larger than the power supply voltage VD ordinarily on the order of 15 V, so that the N type semiconductor region itself constituting the photoelectric conversion cell is caused to be put into a depletion condition whereby all the signal electric charge is removed into the N.sup.-- semiconductor substrate 1.
In parallel to the above mentioned operation, the unnecessary electric charges existing in the vertical electric charge transfer sections 103, are simultaneously transferred towards the horizontal electric charge transfer section 300 by for example four-phase clock pulses .phi.V1to .phi.V4. At this time, the horizontal electric charge transfer electrodes 17H1, 19H1and 17H2, 19H2are supplied with .phi.H1and .phi.H2, respectively, which alternately and exclusively assume the high level voltage VH and the low level voltage VL, as shown in FIG. 6. In addition, an excessive electric charge which cannot be stored in the horizontal electric charge transfer section 300, is caused to move beyond a potential .PSI.B of the potential barrier formed to become deeper than a potential .PSI.VH formed in the vertical-horizontal junction section 200 (shown in FIGS. 3A and 3B) so that the excessive electric charge is absorbed and removed into the N.sup.++ semiconductor region 12 of the unnecessary electric charge exhausting section 500 adjacent to the potential barrier section 400, in order to prevent the electric charges from being returned back to the vertical electric charge transfer sections 103. Incidentally, since the transfer channel 14 of the vertical-horizontal junction section 200 has the width on the order of 2 .mu.m to 3 .mu.m and the same impurity concentration as those of the N type semiconductor regions 6 and 15, the potential .PSI.VH becomes shallower than a potential .PSI.HHS of the electric charge storage region 6 of the horizontal electric charge transfer section 300, because of a narrow channel effect.
Thereafter, the unnecessary electric charge remaining in the horizontal electric charge transfer section 300, is absorbed and removed into the N.sup.+++ semiconductor region 9 of the reset drain provided at the end of the horizontal electric charge transfer section 300, by an ordinary high speed transfer operation of the horizontal electric charge transfer section driven by the two-phase clocks .phi.H1and .phi.H2as shown in FIG. 6.
Succeedingly, the signal electric charge stored in each photoelectric conversion cell 101, corresponding to the amount of light injected for a predetermined time period, is read out to the vertical electric charge transfer section 103, and thereafter, is further vertically transferred through the vertical electric charge transfer section 103, so that the signal electric charges are transferred to the horizontal electric charge transfer section 300 in units of one horizontal line, and are further horizontally transferred through the horizontal electric charge transfer section 300 and are outputted to the output amplifier 302 through the electric charge detection section 301 including the floating diffused region 8 and the output gate electrode 17OG.
Referring to FIGS. 7A to 7L, there are sectional views illustrating a method for manufacturing the prior art solid state image sensor having the above mentioned structure. FIGS. 7A, 7C, 7E, 7G, 7I and 7K are sectional views taken along the line Y--Y in FIG. 1, and FIGS. 7B, 7D, 7F, 7H, 7J and 7L are sectional views taken along the line X--X in FIG. 1. In addition, FIGS. 7A and 7B, FIGS. 7C and 7D, FIGS. 7E and 7F, FIGS. 7G and 7H, FIGS. 7I and 7J, and FIGS. 7K and 7L show the same steps, respectively.
As shown in FIGS. 7A and 7B, a P-well layer 2 is formed on an N.sup.-- semiconductor substrate by implanting boron ions through a thin oxide silicon film 21 formed on the N.sup.-- semiconductor substrate 1, or by conducting introduction of boron ions and a thermal diffusion. The P-well layer 2 is used to constitute the vertical electric charge transfer sections and the horizontal electric charge transfer section. Succeedingly, for the device isolation, a P.sup.++ semiconductor region 4 is formed and a thick silicon oxide film 3 is formed by a selective oxidation.
Thereafter, as shown in FIGS. 7C and 7D, phosphorus ions are implanted through the thin oxide silicon film 21 by using the thick silicon oxide film 3 and a patterned photoresist film (not shown) as a mask, so that an N-type semiconductor region 6 is formed in a region in which the transfer channel of each vertical electric charge transfer section 103 is to be formed, and in a region in which the transfer channel of the horizontal electric charge transfer section 300, the potential barrier section 400 and the unnecessary electric charge exhausting section 500 are to be formed.
Then, as shown in FIGS. 7E and 7F, phosphorus ions are implanted through the thin oxide silicon film 21 by using the thick silicon oxide film 3 and a patterned photoresist film 22 as a mask, so that an N.sup.++ semiconductor region 12 is formed to constitute the unnecessary electric charge exhausting section 500.
Further, as shown in FIGS. 7G and 7H, boron ions are implanted through the thin oxide silicon film 21 by using a patterned photoresist film 23 as a mask, so that an N.sup.- semiconductor region 11 is formed to constitute the potential barrier section 400.
Thereafter, by maintaining the thin oxide silicon film 21 or by removing the thin oxide silicon film 21 and newly forming a thin oxide silicon film 16 as shown in FIGS. 7I and 7J, patterned first conductive electrodes are formed, which become transfer electrodes of the vertical electric charge transfer section 103 and the horizontal electric charge transfer section 300 (specifically, first horizontal electric charge electrodes 17H1, 17H2, an output gate electrode 17OG (shown in FIG. 4A) and a reset gate electrode 17R (shown in FIG. 4A) of the horizontal electric charge transfer section 300). Then, by using a photoresist film (not shown) having an opening on the region in which the horizontal electric charge transfer channel is to be formed, and the first horizontal electric charge electrodes 17H1, 17H2, as a mask, boron ions are implanted through the thin oxide silicon film 16 to form N.sup.- semiconductor regions 5 which constitute an electric charge barrier region of the horizontal electric charge transfer section.
As shown in FIGS. 7K and 7L, a silicon oxide film 18 is formed to cover the first conductive electrodes, and then, patterned second conductive electrodes are formed, which become transfer electrodes of the vertical electric charge transfer section 103 and the horizontal electric charge transfer section 300 (specifically, second horizontal electric charge electrodes 19H1, 19H2of the horizontal electric charge transfer section 300).
Furthermore, phosphorus ions are implanted by using as a mask a pattern photoresist (not shown), the thick silicon oxide film 3, the output gate electrode 17OG and the reset gate electrode 17R, to form a floating diffused region 8 (shown in FIG. 4A), a reset drain 9 (shown in FIG. 4A) and an N.sup.+++ semiconductor region 13 (shown in FIG. 5A).
Thereafter, an interlayer insulator film (designated with Reference Numeral 20 in FIGS. 4A and 5A) are formed on the first and second conductive electrodes by a thermal oxidation or a CVD process. After the interlayer insulator film is formed, a metal film (not shown) for a light blocking and a wiring is deposited by sputtering, and then, patterned to form light blocking films and metal wiring conductors. Thereafter, a protection silicon oxide film is formed. Thus, the prior art solid state image sensor is obtained.
In the above mentioned prior art solid state image sensor having the unnecessary electric charge exhausting section provided adjacent to the horizontal electric charge transfer section with the potential barrier section being between the unnecessary electric charge exhausting section and the horizontal electric charge transfer section, the vertical electric charge transfer sections are located at one side of the horizontal electric charge transfer section, and bus lines (not shown) for supplying the pulse voltages .phi.H1and .phi.H2to the first and second horizontal transfer electrodes of the horizontal electric charge transfer section, are required to be located at the side of the horizontal electric charge transfer section opposite to the side of the horizontal electric charge transfer section coupled to the vertical electric charge transfer section. Therefore, it is necessary to form the transfer channel of the horizontal electric charge transfer section, the potential barrier section and the unnecessary electric charge exhausting section, under the first and second horizontal transfer electrodes of the horizontal electric charge transfer section. As a result, the number of manufacturing steps is disadvantageously larger than the number of manufacturing steps for a prior art solid state image sensor having no unnecessary electric charge exhausting section.
Furthermore, it was disadvantageously necessary to form the N.sup.- semiconductor region 11 which constitutes the potential barrier required to be formed under the first conductive electrode, in a step different from a step for forming the N.sup.- semiconductor region 5 which constitutes the electric charge barrier in the horizontal electric charge transfer section and which is required to be formed in a self-alignment with the first conductive electrode by using the first conductive electrode as a mask.
In addition, the N.sup.- semiconductor region 11 (constituting the potential barrier and the N.sup.- semiconductor region 5 constituting the electric charge barrier in the horizontal electric charge transfer section, are desired to have the same impurity concentration and the same potential. However, because of variation in the manufacturing process, when the potential .PSI.B of the potential barrier becomes shallower than the potential .PSI.HB of the electric charge barrier in the horizontal electric charge transfer section (.DELTA..PSI.=.PSI.HHB-.PSI.B&gt;0, differently from the situation shown in FIG. 3B), the unnecessary electric charges which has remained in the electric charge barrier region, cannot be completely removed during one horizontal scan period, and therefore, an extra time (extra transfer times) is required to completely remove the unnecessary electric charges. Because of this, it was necessary to form to the effect that the potential .PSI.B of the potential barrier is deeper than the potential .PSI.HHB of the electric charge barrier in the horizontal electric charge transfer section (.DELTA..PSI..ltoreq.0), with the result that the electric charge transfer capacity of the horizontal electric charge transfer section is adversely restricted by the height of the potential barrier (.PSI.B-.PSI.HHS), and further has a variation.